Many tunnel diode memory designs have been previously described. Miller et al., in U.S. Pat. No. 3,120,653, granted Feb. 4, 1964, described pairs of tunnel diodes resistively coupled to data lines, which may be used to program the tunnel diode “latch” by “clocking” the power supply. Matsukawa, in U.S. Pat. No. 4,573,143, granted Feb. 25, 1986, describes pairs of tunnel diodes being programmed with data lines coupled to perpendicular word line gated transistors. Lin, in U.S. Pat. No. 5,267,193, granted Nov. 30, 1993, describes a multi-valued memory cell consisting of two pairs of back-to-back tunnel diodes in series. In spite of their compact size and their high speed, in the past, pairs of tunnel diodes may have been difficult to electrically match, making defect-free large memories difficult to manufacture.
Capacitive coupling to data lines has been previously described by Gunn in U.S. Pat. No. 3,196,405, granted Jul. 20, 1965, where each bit of memory consists of pairs of regular semiconductor diodes sandwiched between a capacitor connected to a data line. Such a structure made use of the variable capacitance of the diode pairs to hold bit values as a capacitive charge in a manner, which may be similar to some Dynamic Random Access Memory (DRAM) designs, whereas the negative resistance characteristic of tunnel diode designs may form “latches” in a manner analogous to Static Random Access Memories (SRAMs).
The inventor, in U.S. patent application Ser. No. 13/454,155, filed Apr. 24, 2012, describes a solar array comprised of an array of visible light wavelength antennas coupled to pairs of ultrahigh speed rectifying tunnel diodes, and the fabrication of such a structure may be comprised entirely of successive depositions and etches performed on a preconfigured stencil, eliminating masking variations, which may thereby minimize the variations in the electrical characteristics of the pairs of diodes. Given the potential high performance, high density and low manufacturing cost, it therefore may be desirable to apply the inventor's techniques to the design and fabrication of a tunnel diode memory.